RISC-V Public Notice for Zc Standard Extensions

We are pleased to announce the start of the public review period for the following proposed standard extensions for the RISC-V ISA:

Zca: Instructions in the C extension that do not include floating point loads and stores.

Zcf – the existing set of compressed single-precision floating-point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp.

Zcd - existing set of compressed double precision floating point loads and memories: c.fld, c.fldsp, c.fsd, c.fsdsp.

Zcb: simple code size logging instructions that are easy to implement on all CPUs

Zcmp: A set of instructions that can be executed as a set of existing 32-bit RISC-V instructions (push/pop and double move)

Zcmt: Adds table jump instructions and also adds CSR JVT

The exam period begins today, October 12, 2022 and ends on November 26, 2022 (inclusive).

This extension is part of the non-privileged specification.

These extensions are described in the PDF specification available at:

which was generated from source available in the following GitHub repository:

To respond to public review, please email your comments to the isa-dev public mailing list or add issues and/or pull requests (PR) at code-size-reduction GitHub repository: . We welcome all input and appreciate your time and effort to help us by reviewing the specifications.

During the public review period, fixes, comments, and suggestions will be collected for consideration by the Code Reduction Working Group. All minor corrections and/or non-controversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the Public Review Summary Report. If there are no issues requiring inconsistent changes to the public review specification, the ISA Unprivileged Committee will recommend that the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the ISA Board. RISC-V administration.

Thanks to all contributors for their hard work.

Kurdish Tariq

Chair, Code size reduction

--

Tariq Kurd |LeaderIP Architect | Codasip UK Design Center |

We are pleased to announce the start of the public review period for the following proposed standard extensions for the RISC-V ISA:

Zca: Instructions in the C extension that do not include floating point loads and stores.

Zcf – the existing set of compressed single-precision floating-point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp.

Zcd - existing set of compressed double precision floating point loads and memories: c.fld, c.fldsp, c.fsd, c.fsdsp.

Zcb: simple code size logging instructions that are easy to implement on all CPUs

Zcmp: A set of instructions that can be executed as a set of existing 32-bit RISC-V instructions (push/pop and double move)

Zcmt: Adds table jump instructions and also adds CSR JVT

The exam period begins today, October 12, 2022 and ends on November 26, 2022 (inclusive).

This extension is part of the non-privileged specification.

These extensions are described in the PDF specification available at:

which was generated from source available in the following GitHub repository:

To respond to public review, please email your comments to the isa-dev public mailing list or add issues and/or pull requests (PR) at code-size-reduction GitHub repository: . We welcome all input and appreciate your time and effort to help us by reviewing the specifications.

During the public review period, fixes, comments, and suggestions will be collected for consideration by the Code Reduction Working Group. All minor corrections and/or non-controversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the Public Review Summary Report. If there are no issues requiring inconsistent changes to the public review specification, the ISA Unprivileged Committee will recommend that the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the ISA Board. RISC-V administration.

Thanks to all contributors for their hard work.

Kurdish Tariq

Chair, Code size reduction

--

Tariq Kurd |LeaderIP Architect | Codasip UK Design Center |

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